An integrated circuit die is subject to a series of tests to ensure that it can operate within the desired parameters. A die which passes these tests is referred to as a known good die (KGD). Dice are manufactured in lots on wafers. Each die is initially probe tested while still on the wafer. Wafer level testing is usually limited to testing for continuity and resistance and sometimes for capacitance and/or inductance. The die typically cannot be statically or dynamically tested under environmental conditions while still on the wafer. Difficulties with access and thermal expansion have presented problems in providing power, ground and signals into and out of a die in the middle of a wafer. For example, testing of a die under power while still on the wafer can cause thermal damage to the other dice on the wafer. As a result, most dice are not further tested prior to sorting. Preferably, a die sliced from the wafer which has passed the probe test is thereafter subject to environmental functional and climatic burn-in testing to make certain that it operates properly under conditions which approximate the worst that it can expect to experience during use.
The burn-in tests involve pre-exposing the dice to anticipated functional and climatic environmental conditions so as to sort out infant mortality and marginal responsive chips. The scope and exposure can include testing for any or all of temperature, time or voltage. Temperature testing can include testing the chip at low (down to -65 degrees Centigrade), ambient (approximately 20 degrees Centigrade) and/or high (up to 175 degrees Centigrade) temperatures. Testing for time can include on-off testing and/or duration testing, for example 24, 48 or 168 hours. Voltage testing can include zero or continuity testing, static testing for power, ground and/or signal levels, dynamic testing for partial or full range performance and testing at greater than specification levels for accelerated stress. In this regard, typical die may be subjected to shock forces, biasing, continuity checks, voltage signal cycling, power surges and high-current thermal shock during burn-in testing.
Currently, most dice are mounted to a package to permit electrical access to the individual die. Although the package can have many different designs, a first level package such as a lead frame package having one of the several standard or conventional lead or pin configurations adopted by the semiconductor industry is typically used. As a result, most test, burn-in, transferring and handling equipment is designed to accommodate only die packages having input and output leads or pins arranged in one of these standard configurations. This standardization not only reduces compatibility problems between packages and circuit boards, but also between packages and test, burn-in, handling and transferring equipment. A die mounted in a nonstandard die package or support structure typically requires costly specialized machinery for testing, burn-in, transferring and/or handling.
Standard single chip packages include the dual in-line package (PIN), the pin grid array package (PGA), the quad flat package (QFP), leaded chip carrier, low lead count metal can package, small outline integrated circuit package (SOIC), ball grid array package (BGA) and metal pin grid array package (MQUAD). The dual inline and pin grid array packages are through hole packages having pins or leads for mounting in a socket or hole in the second level package; the quad flat package is a surface mounted package having leads or pads meant for surface mounting to the second level package.
Mounting a die within a package typically involves attaching the die within a socket formed in the package by die bonding with a suitable medium such as epoxy or filled polymer. The interconnect or wire bond pads of the die are electrically connected to the package leads with electrical interconnects permanently attached to the wire bond pads such as by wire bonding, lead bonding or soldering. A lid is usually mounted, often by soldering, over the socket once the die has been attached therein. Once burn-in has been completed, the lid is desoldered to permit access to the die. If the die does not perform properly under the burn-in tests, the die and package are usually discarded. Although methods exist for salvaging packages for reuse, these methods have not usually proven cost effective.
Apparatus or fixtures have been provided for performing burn-in testing on discrete nonpackaged dice. Some of these fixtures are designed to make electrical connections with the integrated circuit of the dice without forming a permanent connection to the wire bond pads. For example, see the apparatus disclosed in U.S. Pat. No. 4,899,107. These apparatus and fixtures, however, have a variety of disadvantageous. For example, the nonstandard test apparatus disclosed in U.S. Pat. No. 4,899,107 requires specialized machinery for use therewith and has not proven altogether satisfactory in operation. In addition, low force nonpermanent connections to wire bond pads have been found to be difficult by the fact that most bond pads cannot withstand a large pressure thereon without disfiguring the bond pad surface so as to impair subsequent wire bonding or without causing subsurface metallization damage.
Other test fixtures require that deleterious bonds of a permanent nature be made to the interconnect pads, or have proven too complicated to manufacture and/or operate. Still other fixtures have been designed for the burn-in testing of dice and include probes and leads etched from one or more films or layers of conductive material deposited onto an elastomeric layer or film mounted to a rigid support plate or other structure. The probes are pressed against the wire bond pads of the die to establish electrical contact with the die to permit testing thereof. These fixtures suffer from difficulties in piercing through the aluminum oxide layer on aluminum wire bond pads to establish electrical contact therewith and excessive loads exerted on the wire bond pads. Similar fixtures suffering from similar disadvantages have probes mounted to a first structure which is compliantly mounted to a second structure.
Certain integrated circuit dice, such as flip chips, are designed for direct placement on a circuit board, substrate or other first or second level package. The interconnect pads on flip chips are aligned on one surface so as to mate with the bond pads on the substrate or circuit board when the chip is flipped over and placed face down. The interconnect pads on the chip or die consist of bond pads provided with drops of solder known as solder bumps which serve to bond the die and substrate pads together.
As with other chips having conventional bond pads, it has proven difficult to make effective electrical contact with a flip chip in an isolated environment, that is apart from a circuit board. Among other things, this is due to the fact that the tolerances for solder bumps are not as small as those for conventional wire bond pads. For these and other reasons, burn-in tests are typically not performed on flip chips. As can be appreciated, the inability to economically and effectively burn-in test flip chips can increase the percentage of defective chips shipped.